The last time I wrote about SkyWater Technology, I described them as a pure-play semiconductor foundry that was great at taking on small projects that required customized processing steps, the type of work that the big silicon chip foundries won’t consider because they would be too disruptive to their operations. I recently had an opportunity to speak with the company’s CEO, Thomas Sonderman, along with Tim Olson, the founder and CEO of Deca Technologies, a SkyWater partner. Now that I understand what they are up to, I think I have changed my mind. They actually plan to lower the entry barriers to advanced multichip packages, democratizing access in the process. That could be a complement to their foundry business, or it could become more important.
Chip Packaging
For a long time, packaging an integrated circuit was just a means to protect the chip, also known as a “die,” by encapsulating it in a supporting case and connecting it to the outside world with electrical contacts. These chips were in turn mounted on printed circuit boards (PCBs) which interconnected them, providing paths for their signals to move around, as well as feeding the power to run them. Most of the innovation took place within the design and manufacturing of the chips, and over time as they got more complicated, designers added more and denser contacts to support more signals and connections.
With billions of transistors on a single chip, that has meant complicated advanced processes for designing and producing them, which has gotten very expensive and risky. This has driven a surge in interest in ways to combine mixed die using different manufacturing processes into a single package. If designers could do that, it would accomplish several things. You could use the expensive advanced processes only for the most performance sensitive pieces, relegating other parts of the design to older and cheaper processes. You could also combine new chips with parts that you have already made that you know work (and are cheap). Putting multiple chips close together in a single package also reduces propagation delays – the time it takes for electrical signals to move between chips, which is significant when you are chasing high performance. Thus advanced packaging can enable innovative mix-and-match combinations that would get to the market much faster with lower risk.
Multichip Packaging Challenges
There are two types of multichip packaging that are getting a lot of attention. The 2.5D approach involves putting multiple chips as close as possible side-by-side on top of a silicon interposer. 3D involves stacking chips on top of each other using vertical interconnects. 3D packaging, while more space efficient, is complex and costly and faces challenge in managing heat dissipation.
Taiwan Semiconductor Manufacturing Company (TSMC), the chip foundry giant, has a 2.5D Chip-on-Wafer-on-Substrate (CoWoS) process that it has been evolving since 2012. The company makes a silicon interposer, a sliver of patterned silicon to which individual die are bonded with solder micro-bumps. Chips like the Nvidia V100 Tensor Core were built with this technology. The interposer has connection points for each of the die that you want to connect as well as the overall package that you put the entire assembly into. This requires precision alignment when you bond all the die. The size of the interposer has also been a limitation. Because it is made using a photolithography process, it is limited by the size of the reticle – the photomask template that is used to produce the patterns. TSMC has “stitched” multiple masks to make larger interposers.
Deca started from a very different place. “We really had the idea of large panels in mind when we started the company,” Olson explained. Their approach is to form copper studs on a finished wafer, saw apart the die (“singulate” them), and then embed them in a mold face up. This package is then encapsulated, and an interconnect pattern is formed on top with an additive process using laser direct imaging (LDI). Olson explained the process was originally driven by the needs of the smartphone industry where engineers wanted more area to connect pins beyond the outline size of the die. This was important because die sizes kept getting smaller with more advanced process nodes, but one still needed the physical ability to connect lots of signals on a PCB.
Deca transferred and licensed their technology to packaging company ASE, who has been using this process for a number of years. It appears within five different chips inside an Apple
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iPhone 14, as well as the iPhone that recently survived the 16,000 foot, 60 mph vertical drop test from that Alaska Airlines
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Boeing 737 Max 9 flight that had the door plug incident (36 G’s at impact, by the way).
What’s cool about the process is that you can make much larger multichip systems because you are not limited by reticle size. This depends on a technology Deca developed that they call Adaptive Patterning.™ When you mechanically embed chips in a molded package, things shift around and the connection pads may not be in exactly the right positions. So Deca puts the molded panel in a high-precision optical scanner and measures the precise position of every die and connection pad. From measurements of the actual positions, they generate in real-time a lithography pattern that they feed to their LDI machine which then creates the connection pattern. They generate a unique interconnect tailored to whatever is fed into the system. This neatly overcomes process variations, and allows them to scale up to potentially very large systems of many different types of chips. It actually feels like you are somewhere between a 2.5D chip package and the ultimate printed circuit board. “The integration of Adaptive Patterning with the industry’s most advanced LDI machines removes the historic barriers separating chip, package and PCB.” Olson explained. “The result is a powerful new set of capabilities without boundaries for chip and system designers of the future.”
SkyWater licensed Deca’s electronic interconnect technology, and received a Department of Defense (DOD) grant earlier this year in partnership with Osceola County, where SkyWater’s Florida facility is located. Together, SkyWater and Deca are implementing a fan-out wafer level packaging line to support multi-chip packaging. According to Sonderman, “This facility will be distinct in that chip designers can use different devices with unique functionality, that are fabricated at SkyWater or elsewhere to create highly customized system-in-package solutions that directly meet their targeted market requirements.” It will have a relatively low setup cost and it can handle a heterogenous mix of chips, so it could democratize access to an important style of advanced packaging. Sonderman added, “That could empower a large number of system builders who don’t have significant volumes yet but want to take advantage of the benefits of fan-out wafer packaging.” It would also be a neat complement to SkyWater’s foundry business. Or maybe it will become more important.
